I. Field of the Disclosure
The technology of the disclosure relates generally to successive approximation register (SAR) analog to digital converters (ADCs), and particularly to clocking SAR ADCs with asynchronous clock signals.
II. Background
Processor-based systems employ analog to digital conversion of signals in connection with performing various functions. One way to achieve such analog to digital conversion is by using a successive approximation register (SAR) analog to digital converter (ADC). The operation of a SAR ADC involves performing successive comparisons of an input voltage signal to a series of generated analog signals during the conversion process. A SAR ADC uses the result of each comparison of the input voltage signal to the generated analog signals to generate a final value of a digital signal.
For example, in a SAR ADC, to convert an input voltage signal to a digital signal, each bit of the digital signal is initially set to a logic low “0” state during a first clock cycle of a clock signal during the conversion process. While still in the first cycle of the clock signal during the conversion process, the SAR ADC sets the most significant bit of the digital signal to a logic high “1” state, but leaves all remaining bits of the digital signal at a logic low “0” state. The SAR ADC converts the updated digital signal to a generated analog signal and compares the input voltage signal to the generated analog signal. If the generated analog signal has a voltage greater than the input voltage signal, the SAR ADC changes the most significant bit from a logic high “1” state to a logic low “0” state. Conversely, if the generated analog signal has a voltage less than the input voltage signal, the SAR ADC leaves the most significant bit set to a logic high “1” state. The SAR ADC successively sets each bit of the digital signal and compares the corresponding generated analog signal to the input voltage signal in this manner during each corresponding clock cycle during the conversion process. Thus, following the final clock cycle of the clock signal during the conversion process, the digital signal generated by the SAR ADC is a digital representation of the input voltage signal.
In this example, the clock signal that clocks the SAR ADC has a synchronous, constant period. As a result, each clock cycle corresponding to the conversion process uses the same amount of time to perform the corresponding comparison. However, the SAR ADC completes each comparison in a time that is inversely related to a voltage difference between the input voltage signal and the generated analog signal. In other words, the SAR ADC completes a comparison in less time when the voltage difference is larger compared to the amount of time to complete a comparison when voltage difference is smaller. Therefore, clocking the SAR ADC using a synchronous clock signal causes some cycles of the conversion process to consume excess time that is not used for generating the digital signal.